In article <2024Mar10.092913@mips.complang.tuwien.ac.at>,   
   Anton Ertl  wrote:   
   >Paul Rubin  writes:   
   >>anton@mips.complang.tuwien.ac.at (Anton Ertl) writes:   
   >>> If implemented well, the slowdown is small in the common case (small   
   >>> integers): E.g., on AMD64 an add, sub, or imul instruction just needs   
   >>> to be followed by a jo which in the usual case is not taken and very   
   >>> predictable.   
   >>   
   >>It might be worse for RISC V.   
   >   
   >It is.  That's a failure of RISC-V.   
      
   As far as I can tell it was a design choice for DEC Alpha and RISC-V.   
   Apparently flags are detrimental to parallelism.   
      
   You can't call that a failure because you don't like it.   
   >   
      
   Groetjes Albert   
   --   
   Don't praise the day before the evening. One swallow doesn't make spring.   
   You must not say "hey" before you have crossed the bridge. Don't sell the   
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