From: krishna.myneni@ccreweb.org   
      
   On 4/1/24 04:21, dxf wrote:   
   > On 1/04/2024 7:03 pm, minforth wrote:   
   >> dxf wrote:   
   >>   
   >>> While your double-shift algorithm produces the correct results (not shown   
   here),   
   >>> the intermediate values presented to each RSHIFT/LSHIFT can be quite   
   out-of-bounds   
   >>> e.g. a shift of 40 and -20 (actually FFFFFFE0) would concern me.  That an   
   'unambiguous'   
   >>> RSHIFT/LSHIFT will mask questionable parameters fed to it and return a   
   result of 0,   
   >>> I for one find problematic.  IMO it were better that RSHIFT/LSHIFT should   
   fail than   
   >>> do this.   
   >>   
   >> Doesn't make sense during fp number addition/subtraction.   
   >   
   > Example?   
   >   
      
   First, there is no negative shift count argument for LSHIFT RSHIFT   
   DLSHIFT or DRSHIFT . The arguments are unsigned.   
      
   For an ieee 754 double precision number, there is an effective distance   
   of 53 bits between the most significant bit and the least significant   
   bit. On a 32-bit system, consider adding 1.0e0 to the number 1.0e10.   
      
   The ieee-754 unbiased base 2 exponents for the two floating point   
   arguments are 0 (for 1.0e0) and 33 (for 1.0e10). This means that adding   
   the two 53-bit significands using two double numbers (two 64-bit numbers   
   on a 32 bit system) requires a relative right shift of 33 bits for the   
   argument 1.0e0.   
      
   Here are the bit patterns for the two significands, along with their   
   base 2 exponents:   
      
   21098765432109876543210987654321098765432109876543210   
   10010101000000101111100100000000000000000000000000000  33   
   10000000000000000000000000000000000000000000000000000  00   
      
   There are 53 bits in each significand, and the 53rd bit is always an   
   implied 1. To add these, we can use 33 DRSHIFT on the one argument to   
   align the significands and add the two double length numbers to obtain   
   the new significand.   
      
   For ieee 754 quad precision, there are 113 bits in the significand, so   
   relative shifts can be as large as 112 bits for addition and subtraction.   
      
   --   
   Krishna   
      
   --- SoupGate-Win32 v1.05   
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