From: anton@mips.complang.tuwien.ac.at   
      
   Paul Rubin  writes:   
   >anton@mips.complang.tuwien.ac.at (Anton Ertl) writes:   
   >> * Division by 0 results in an ambiguous condition.  There would be   
   >>   little gain from requiring that it traps.  OTOH, the cost would also   
   >>   be small.   
   >   
   >The trap would require some extra code on risc-v.   
      
   Sure, and on ARM T32 and ARM A64, and on Power, and several EOLed   
   architectures.  The cost is still small.  The gforth engine on RISC-V   
   has:   
      
   see /s   
   Code /s   
          15D42:   sd      s9,$50(s10)   
          15D46:   addi    s9,s9,8   
          15D48:   ld      s8,0(s11)   
          15D4C:   li      a5,-1   
          15D4E:   ld      s6,8(s11)   
          15D52:   addi    s7,s11,8   
          15D56:   bne     s8,a5,$15D68   
          15D5A:   slli    a5,a5,$3F   
          15D5C:   bne     s6,a5,$15D72   
          15D60:   li      a0,$-B   
          15D62:   jal     ra,$24EA6   
          15D66:   j       $15D72   
          15D68:   bne     s8,zero,$15D72   
          15D6C:   li      a0,$-A   
          15D6E:   jal     ra,$24EA6   
          15D72:   div     s6,s6,s8   
          15D76:   mv      s11,s7   
          15D78:   sd      s6,0(s7)   
          15D7C:   ld      a4,0(s9)   
          15D80:   jr      a4   
   end-code   
      
   This checks for both division by zero and overflow on division   
   (minint/-1).  The division by zero check is:   
      
          15D68:   bne     s8,zero,$15D72   
          15D6C:   li      a0,$-A   
          15D6E:   jal     ra,$24EA6   
      
   The overflow check is:   
      
          15D4C:   li      a5,-1   
          15D56:   bne     s8,a5,$15D68   
          15D5A:   slli    a5,a5,$3F   
          15D5C:   bne     s6,a5,$15D72   
          15D60:   li      a0,$-B   
          15D62:   jal     ra,$24EA6   
      
   The jal performs a throw, with the argument in a0.  Throw code $-A is   
   "division by zero", $-B is "result out of range".   
      
   This probably would be more efficient on an in-order core like the U74   
   if the div instruction was moved to before the checks (with   
   appropriate register renaming of the result), but if we do the   
   reordering in the C code, there is the danger that some gcc version   
   will "optimize" one or both checks away (the joys of undefined   
   behaviour).  In theory gcc could to the reordering, but it obviously   
   does not do so.   
      
   - anton   
   --   
   M. Anton Ertl  http://www.complang.tuwien.ac.at/anton/home.html   
   comp.lang.forth FAQs: http://www.complang.tuwien.ac.at/forth/faq/toc.html   
        New standard: https://forth-standard.org/   
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