From: no.email@nospam.invalid   
      
   anton@mips.complang.tuwien.ac.at (Anton Ertl) writes:   
   > There is the E subspecification of the RISC-V specification with 16   
   > registers.  I don't know if anybody has implemented this.   
      
   The CH32V003 uses it and is of some interest as a Forth target.  It has   
   16k of flash and 2k of ram.   
      
   https://www.cnx-software.com/2022/10/22/10-cents-ch32v003-risc-v   
   mcu-offers-2kb-sram-16kb-flash-in-sop8-to-qfn20-packages/   
      
   > More efficient in code size.  In instruction execution, typically the   
   > same speed.   
      
   https://dl.acm.org/doi/10.1145/3578360.3580261 indicates some minor   
   speed differences, not always favorable.   
      
   --- SoupGate-DOS v1.05   
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