In article <2025Mar27.084835@mips.complang.tuwien.ac.at>,   
   Anton Ertl  wrote:   
   >Paul Rubin  writes:   
   >>albert@spenarnc.xs4all.nl writes:   
   >>> (I get 30 registers in RISCV that can serve as a stack pointer.)   
   >   
   >All 31 can serve as a stack pointer, but not all at the same time.   
   >You want at least two registers for temporary values, for implementing   
   >a word such as "+".  And you typically want to keep the top-of-stack   
   >of many stacks in a register, too.  Or several stack items.   
   >   
   >>In some models of the RISCV, only 14, I think.   
   >   
   >There is the E subspecification of the RISC-V specification with 16   
   >registers.  I don't know if anybody has implemented this.   
   >   
   >>And in almost all   
   >>models, 8 of them are more efficient to address than the rest, because   
   >>of the compressed instruction format.   
   >   
   >More efficient in code size.  In instruction execution, typically the   
   >same speed.   
      
   The orange pi RV2 is a risc with 8 Gbyte at euro 64 with NVMe slots, wifi,   
   sdcard,   
   gbyte internet, usb, hdmi, mipi etc. and still the 26 pin Raspberry 1 slot.   
      
   Worrying about code size is so seventies unless you are into 10 cent   
   riscv embedded soc's (see noforth).   
      
   >   
   >- anton   
      
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