From: dxforth@gmail.com   
      
   On 16/07/2025 12:09 pm, minforth wrote:   
   > Am 15.07.2025 um 17:25 schrieb LIT:   
   >>> Now riscv is the future.   
   >>   
   >> I don't know. From what I learned, RISC-V   
   >> is strongly compiler-oriented. They wrote,   
   >> for example, that it lacks any condition codes.   
   >> Only conditional branches are predicated on   
   >> examining the contents of registers at the time   
   >> of the branch. No "add with carry" nor "subtract   
   >> with carry". From an assembly point of view, the   
   >> lack of a carry flag is a PITA if you desire to   
   >> do multi-word mathematical manipulation of numbers.   
   >>   
   >> So it seems, that the RISC-V architecture is intended   
   >> to be used by compilers generating code from high level   
   >> languages.   
   >   
   > I read somewhere:   
   > The standard is now managed by RISC-V International, which   
   > has more than 3,000 members and which reported that more   
   > than 10 billion chips containing RISC-V cores had shipped   
   > by the end of 2022. Many implementations of RISC-V are   
   > available, both as open-source cores and as commercial   
   > IP products.   
   >   
   > You call that compiler-oriented???   
      
   It depends on how many are being programmed by the likes of GCC.   
   When ATMEL hit the market the manufacturer claimed their chips   
   were designed with compilers in mind.  Do Arduino users program   
   in hand-coded assembler?  Do you?  It's no longer just the chip's   
   features and theoretical performance one has to worry about but   
   the compilers too.   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)