From: anton@mips.complang.tuwien.ac.at
albert@spenarnc.xs4all.nl writes:
>The document I have of the RISCV instruction set doesn't specify
>symmetric or floored division for the DIV instruction, either way!
The official documentation is "The RISC-V Instruction Set Manual
Volume I -- Unprivileged Architecture". A somewhat recent version
says (in 'Chapter 13. "M" Extension for Integer Multiplication and
Division, Version 2.0'):
|DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned
|integer division of rs1 by rs2, rounding towards zero. REM and REMU
|provide the remainder of the corresponding division operation. For
|REM, the sign of a nonzero result equals the sign of the dividend.
I.e., DIV is symmetric, and REM gives its remainer.
Here are Gforth's /s, /f, mods and modf (/ is /f and mod is modf):
see /s
Code /s
15B64: addi s5,s5,8
15B66: ld a5,8(s6)
15B6A: addi s6,s6,8
15B6C: div s9,a5,s9
15B70: ld a5,0(s5)
15B74: jr a5
end-code
ok
see /f
Code /f
15AA4: addi s5,s5,8
15AA6: ld a5,8(s6)
15AAA: mv a4,s9
15AAC: addi s6,s6,8
15AAE: xor a3,a5,s9
15AB2: div s9,a5,s9
15AB6: bge a3,zero,$15AC6
15ABA: rem a5,a5,a4
15ABE: sltu a5,zero,a5
15AC2: sub s9,s9,a5
15AC6: ld a5,0(s5)
15ACA: jr a5
end-code
ok
see mods
Code mods
15B76: addi s5,s5,8
15B78: ld a5,8(s6)
15B7C: addi s6,s6,8
15B7E: rem s9,a5,s9
15B82: ld a5,0(s5)
15B86: jr a5
end-code
ok
see modf
Code modf
15ACC: addi s5,s5,8
15ACE: ld a4,8(s6)
15AD2: mv a5,s9
15AD4: addi s6,s6,8
15AD6: xor a3,a4,s9
15ADA: rem s9,a4,s9
15ADE: bge a3,zero,$15AE8
15AE2: beq s9,zero,$15AE8
15AE6: add s9,s9,a5
15AE8: ld a5,0(s5)
15AEC: jr a5
end-code
>Note: instruction set manuals for RISCV are hard to come by.
Duckduckgo gave me the link above as first hit when I asked for "the
risc-v instruction set manual volume i: unprivileged isa". This very
specific request was suggested by my browser when I typed in "risc-v
instruction set manual".
>Instead of an absolute autoritive instruction manual for i86
>by Intel, are there now competing, possibly incomplete manuals by
>each supplier?
AMD documents what they do, and Intel document what they do. That has
been the case since at least AMD introduced AMD64 was introduced in
2003, possibly earlier (e.g., with 3DNow and SSE). In my practice,
this has not been a problem. The same code usually works on both
Intel and AMD CPUs; and if you use some instruction set extensions,
and it works on one Intel processor, it may fail on the next one.
>So should I continue with changing from symmetric to floored?
How does your uncertainty over the meaning of the instruction set have
any relevance for that? If you don't know what the division
instructions do, you cannot use them for any kind of division word,
whether symmetric or floored. Fortunately, we do know it.
- anton
--
M. Anton Ertl http://www.complang.tuwien.ac.at/anton/home.html
comp.lang.forth FAQs: http://www.complang.tuwien.ac.at/forth/faq/toc.html
New standard: https://forth-standard.org/
EuroForth 2025 CFP: http://www.euroforth.org/ef25/cfp.html
EuroForth 2025 registration: https://euro.theforth.net/
--- SoupGate-Win32 v1.05
* Origin: you cannot sedate... all the things you hate (1:229/2)
|
