XPost: alt.folklore.computers, openwatcom.users.c_cpp   
   From: david.brown@hesbynett.no   
      
   On 04/11/2025 18:32, Scott Lurndal wrote:   
   > scott@slp53.sl.home (Scott Lurndal) writes:   
   >> Peter Flass  writes:   
   >>> On 11/4/25 08:20, Scott Lurndal wrote:   
   >>>> Kaz Kylheku <643-408-1753@kylheku.com> writes:   
   >>>>> On 2025-11-03, Peter Flass  wrote:   
   >>>>>> On 11/3/25 13:24, Lynn McGuire wrote:   
   >>>>>   
   >>>>> When I saw this subject line, I thought it was some necroposting to   
   >>>>> threads from 1990.   
   >>>>>   
   >>>>> Someone still cared about segmented x86 shit in 2010 (even if 32 bit)?   
   >>>>   
   >>>> There are still people on the internet who swear that the 286 is   
   >>>> better than sliced bread and refuse to recognize that modern   
   >>>> architectures are superior.   
   >>>>   
   >>>   
   >>> I was thinking, are there any segmented architectures today?   
   >>   
   >> Only in emulation (see Unisys Clearpath, for example).   
   >   
   > Although it's worth pointing out that harvard architectures   
   > still exist (e.g. CEVA DSPs)   
      
   Yes, but Harvard architectures are a very different matter from   
   segmented architectures.  "Real" Harvard architecture processors have   
   different instructions for accessing different memory spaces - such as   
   on the AVR microcontrollers, the instructions for reading ram and   
   reading program flash are totally different, and you cannot execute code   
   from ram.   
      
   Segmented architecture just means that the actual address is formed by a   
   scaled segment register (or value) combined with an offset or pointer   
   register (or value).   
      
   There are plenty of segmented architectures in the world of small   
   microcontrollers, where the "pointer" might be 8-bit, 16-bit, or a pair   
   of 8-bit registers, and it is combined with a bank or segment register   
   so that the device can use more than 64KB memory.  These devices may or   
   may not be Harvard.  Fortunately, most of these are considered legacy   
   devices.   
      
   > and the low-power ARM   
   > M-series core 32-bit physical address space is   
   > divided into 28-bit regions some of which may   
   > provide programmable windows into alternate address spaces   
   > in a fashion very similar to segmentation.   
   >   
      
   All the ARM Cortex-M cores have 32-bit linear memory spaces.  There is   
   no segmentation.  Different parts of the memory space are used for   
   different purposes (ram, flash, peripherals, off-chip memory, etc.), and   
   there can be lots of different memory-mapped devices placed at different   
   points in the memory spaces.  But all access is via 32-bit addresses in   
   32-bit registers, without any segmentation registers.  (And I have never   
   seen a Cortex-M device with programmable windows or addresses - indeed,   
   I believe the Cortex-M core documentation specifies some memory ranges   
   explicitly.  Memory protection units can be programmable to give   
   different accesses, writes and cachability attributes to different   
   regions, but that's another matter.)   
      
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