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   comp.lang.c      Meh, in C you gotta define EVERYTHING      243,242 messages   

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   Message 241,814 of 243,242   
   David Brown to Scott Lurndal   
   Re: 16:32 far pointers in OpenWatcom C/C   
   06 Nov 25 08:51:37   
   
   XPost: alt.folklore.computers, openwatcom.users.c_cpp   
   From: david.brown@hesbynett.no   
      
   On 05/11/2025 16:15, Scott Lurndal wrote:   
   > David Brown  writes:   
   >> On 04/11/2025 23:04, Scott Lurndal wrote:   
   >>> David Brown  writes:   
   >>>> On 04/11/2025 18:32, Scott Lurndal wrote:   
   >>>   
   >>>> .  (And I have never   
   >>>> seen a Cortex-M device with programmable windows or addresses - indeed,   
   >>>> I believe the Cortex-M core documentation specifies some memory ranges   
   >>>> explicitly.   
   >>>   
   >>> I have used Cortex-M devices with programmable windows   
   >>> in the physical address space.   
   >>   
   >> OK.  I have not, but I haven't used the newer Cortex-M cores as yet, so   
   >> it could well be a new feature.   
   >   
   > It is not necessarily a feature of the M7 core itself, but rather   
   > the glue logic around it - particularly the logic that interfaces   
   > to the "system bus" to which the M7 core is interfaced.   That logic   
   > is under the control of the SoC designer and can easily have   
   > external registers that are programmed to specify how to route   
   > accesses from the M7, including to large regions of DRAM;   
   > consider a maintenance processor on a 64-bit server that needs   
   > access to the server DRAM space for RAS purposes.   
   >   
      
   Fair enough, now I see what you are getting at.  Yes, once you are   
   outside the Cortex-M core and key ARM-supplied components (like the   
   interrupt controller), you as a SoC designer are free to do what you   
   like.  And if you have a 32-bit processor that needs access to a 64-bit   
   address space, you are going to have to do some kind of windowing or   
   segmenting.   
      
   In the SoC's I have used where 64-bit Cortex-A processors are combined   
   with a Cortex-M core for security purposes, booting, or for better   
   real-time control of peripherals, the Cortex-M device does not have   
   direct access to the 64-bit memory space.  It has access to the   
   peripherals, some dedicated memory, and a message-passing interface with   
   the Cortex-A cores.   
      
   But in your work, you probably see more variety and more possibilities   
   for these things - I only get to use the chips someone else has made!   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)   

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