From: david.brown@hesbynett.no   
      
   On 09/11/2025 10:46, Michael S wrote:   
   > On Sat, 8 Nov 2025 00:00:06 -0000 (UTC)   
   > cross@spitfire.i.gajendra.net (Dan Cross) wrote:   
   >   
   >>   
   >>> I'd say, if you (SOC designer) absolutely have to play these games,   
   >>> just use Cortex-M4.   
   >>   
   >> Sometimes you really do need an M7 class part.   
   >>   
   >> 	- Dan C.   
   >>   
   >   
   > Somehow I suspect that [at the same clock frequency] M4 could access   
   > uncached memory faster that M7. May be, even significantly faster.   
   >   
      
   I suspect you would be wrong.  The M7 can do more per clock than the M4,   
   has wider buses, and has support for direct data and instruction   
   memories with their own dedicated buses.  I can appreciate the gut   
   feeling that because there is the option of caching accesses, that extra   
   functionality may slow down accesses when the cache is not used, but I   
   don't believe that happens on the M7.  And everything other than the   
   accesses themselves (the loads, stores, address increments, looping,   
   etc.) can be quite a lot faster at the same clock speed.   
      
   But as you say, public data on timings is limited - and even when the   
   data on the core is available, timings can be very dependent on details   
   of the implementation and connections outside the core.   
      
   We could always appeal to authority - Scott's company knows what they   
   are doing, have access to far more detailed information and technical   
   assistance from ARM than we do, and have picked an M7 rather than an M4.   
     But speculation is more fun :-)   
      
   > Unfortunately, info about M7 instructions timing does not appear to be   
   > public.   
   >   
   > If one needs something like DP floating or when uncached accesses are   
   > only small part of the job and the rest of the load is compute   
   > -intensive then I can see how M7 could look attractive vs M4.   
   > But personally in such case I'd start to look for non-Cortex-M solution.   
   > May be R4, although I don't like it. May be A5. In huge SoCs of sort   
   > Scott is working on - A34 or even 510. Plus, another M4 to handle more   
   > typical MCU tasks.   
   >   
   >   
   >   
   >   
      
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