From: skybuck2000@hotmail.com   
      
   Two postings:   
      
   Posting 1:   
      
   Skybuck's Universal Memory Architecture (Invention by Skybuck Flying on 18   
   october 2021)   
      
   The Problem:   
      
   To use Universal Fields (Universal Codes) memory needs to be able to grow.   
      
   Currently no architecture exists which allows data fields/memory fields to   
   grow.   
      
   The Solution:   
      
   Imagine the film tron where these motor cycles draw these walls/lines the   
   motorcyclist has to draw these walls/lines and trap the other player   
   by making him slam into a wall. There is also a computer game based on it   
   called "snake", where snakes grow by eating pixels. As the snake grows   
   it describes a line, the snake is free to move left, right, up, down but may   
   not end up on a square already taken by any other snake.   
      
   Imagine storing a data bit on each square as the snake grows.   
      
   These lines/walls that are formed by the snake/motor cyclist can be considered   
   a "data tape".   
   Alan Turning described the need for an imaginary data tape of endless length   
   to be able to do "universal computing" and "universal machines".   
      
   To be able to know where the snake originated, the start of data tape has to   
   be recorded. This would be a 2D or 3D or ND coordinate.   
      
   For example SnakeSourceX,SnakeSourceY this would be the tail of the snake,   
   which can also be described as SnakeTailX,SnakeTailY   
      
   To be able to know where the head of the snake is so it can be made to grow,   
   the end of the data tape has to be recorded.   
      
   For example SnakeDestX,SnakeDestY this would be the head of the snake, which   
   can also be described as SnakeHeadX,SneakHeadY.   
      
   A processor could number the snakes and refer to them by numbers, basically   
   each snake is a data field.   
      
   To encode instructions for the processor, the instructions codify on which   
   snake/data field the instruction operates.   
      
   To store these data fields there could be an additional memory structure which   
   stores these snake coordinates as follows:   
      
   SnakeReferenceMemoryStructure:   
      
   SnakeNumber, SnakeSourceX, SnakeSourceY, SnakeDestX, SnakeDestY   
      
   For example:   
   0, 100, 500, 40, 30   
   1, 10, 20, 100, 200   
   2, 60, 70, 30, 40   
   3, 101, 302, 35, 67   
   4, 56, 75, 45, 34   
      
   The processor can then refer to data fields by SnakeNumber, so that   
   instructions stay consist and entire snakes can be moved around in memory in   
   case a snake crashes   
   into a wall.   
      
   To store data bits into the snake each memory cell/unit has to have the   
   following properties:   
      
   DataBit On/Off		(1 transistor)   
   DirectionBit0 On/Off    (1 transistor)   
   DirectionBit1 On/Off    (1 transistor)   
   ConnectedBit On/Off     (1 transistor) (optional)   
      
   Each 2D memory cell therefore consists out of these 4 transistors.   
      
   The data bit transistor records the information data bit 0 or 1.   
      
   The DirectionBit0 and DirectionBit1 describe in which direction the snake grew   
   and therefore to which other memory cell the current memory cell is   
   "connected".   
   DirectionBit0, DirectionBit1   
   00 = up   
   01 = right   
   10 = down   
   11 = left   
      
   The connected bit is optional, based on universal codes the software itself   
   could decide if another snake cell follows the last read snake cell, however   
   for allocation   
   purposes/algorithms it may be usefull to codify this information directly into   
   the memory units and thus ConnectedBit describes if any cell follows the   
   current one.   
      
   ConnectedBit   
   0 = head of snake/last cell   
   1 = intermediate cell   
      
   The challenge for the computer systems and memory manager is to allocate   
   snakes as efficiently as possible, basically to play the game snakes as   
   efficiently as possible.   
   Algorithms could be developed or perhaps already exist that excell in this.   
   Different allocations, direction strategies and starting points could be tried.   
      
   In the event that a snake/data tape crashes into a wall, can no longer grow an   
   "exception" like mechanism is thrown.   
      
   The processor or memory manager which is responsible for the growing of data   
   tapes/snakes throws an exception like event:   
      
   Describing which snake crashed, plus optionally source and dest information   
   for quick reference or it can be looked up later in the snake memory reference   
   structure by   
   snake number.   
      
   Event generated:   
   Snake X crashed   
      
   Or more advanced event:   
   Snake X, SnakeSourceX,SnakeSourceY,SnakeDestX,SnakeDestY crashed.   
      
   however to make sure the information is consistent perhaps it's better to   
   consult the snake memory reference in the event handler to be sure, perhaps   
   this would make programmers of such event handlers feel more at ease that they   
   have the correct/most recent information, it is more of an emotional   
   consideration, but could also prevent race conditions/race information in case   
   maybe something else modified it in between the event generation and event   
   handler.   
   Preferably none of the snake information/structures/data is changed in between   
   event firing and event handling.   
      
   A computer instruction could be encoded as follows, just an example:   
      
   Operation Codes   
   No Operation = 0   
   Copy = 1   
   Addition = 2   
   Subtraction = 3   
   Multiply = 4   
   Division = 5   
   Jump = 6   
      
   Addressing Modes   
   0 = constants   
   1 = direct addressing   
   2 = indirect addressing   
      
   Instructions:   
   Operation Code, Source Addressing Mode, Source Data Field, Dest Addressing   
   Mode, Dest Data Field   
      
      
   The following pascal pseudo code will be translated into instructions below:   
      
   var   
     Counter : TDataField;   
     Value : TDataField;   
      
   begin   
     Counter := 0;   
     Value := 5;   
      
     while true do   
     begin   
       Counter := Counter + Value;   
     end;   
      
   end;   
      
   Compiler outputs:   
      
   Counter = data field 0   
   Value = data field 1   
      
   Assembly instructions:   
      
   // copy constant 0 to data field 0   
   copy, 0, 0, 1, 0   
      
   // copy constant 5 to data field 1   
   copy, 5, 0, 1, 1   
      
   // add value to counter   
   add, 1, 1, 1, 0   
      
   // jump to previous instruction   
   jump -1   
      
   Hardware wise each "memory unit" must be readable, writeable and addressable.   
   Each memory unit contains 4 transistors as described above.   
      
   I imagine a grid of memory units each with 4 transistors. Each memory unit is   
   connected to a memory bus and address busses, one address bus for each   
   coordinate/dimension.   
      
   To manipulate a memory unit the hardware has to be able to do the following:   
      
   put coordinate x on the x bus.   
   put coordinate y on the y bus.   
   read/write the transistors, this would imply a 4 data bit bus, or just a 1   
   data bit bus and each transistor is read in sequence.   
      
   A more complex memory unit could be constructed so that a processor only   
   read/write 1 bit at a time, like a pci express lane, software is responsible   
   for   
   decoding the communication.   
      
   A benefit of this could be less wires on motherboards, and more placement of   
   individual memory chips, possibly for multi-core/many-core scenerios where each   
      
   [continued in next message]   
      
   --- SoupGate-Win32 v1.05   
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