From: anthonypaulo@gmail.com   
      
   Hey guys, I've been going over some of the timings for writing data from a   
   peripheral card on to the Apple IIe bus and just when I think I have it, I get   
   confused again. This is for an accelerator I'm working on that replaces the   
   6502, and it seems to be    
   working for all reads but some errors on the writes so I want to make sure I   
   have it right. I'm using a IIgs for testing but want to make this work across   
   the range of Apple IIs if possible.   
      
   In the DMA tech note for the IIe it says that the data bus is valid until   
   Phase 0 falls, and even presents a write scenario where you can gate your   
   write using the 7M signal and hold it *until* Phase 0 falls, but in Sather's   
   IIe book pages 4-7 and 4-8 it    
   states a couple of times that write is held valid for some time *after* Phase   
   2 falls, and Phase 2 falls in worst-case 65ns after Phase 0 falls, which means   
   I have to hold the write for some time after Phase 0 falls. I know I must be   
   reading this wrong    
   so would someone enlighten me?   
      
   I'd like my peripheral-card read/write to work across the Apple II range so   
   I'm wondering if anyone has any timing data on when it's safe to start   
   fiddling with the Address and Data buses and R/W line and when they need to be   
   held stable and valid.   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)