From: anthonypaulo@gmail.com   
      
   In the Apple IIe #2 tech notes for DMA, they state the following:   
      
   "...there will be some skew between edges of the 7 M clock and the timing   
   signals from the PAL, such as the edges of 0o or 01. This skew means the 7 M   
   clock edge may rise as much as 20 ns before, or 5 ns after, the 0o falling   
   edge. "   
   Is this skew only at the 0o falling edge? I ask because I'm using the 7m for   
   timing when to read/write.   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)