From: charlieDOTd@verEYEzon.net   
      
   On 8/4/2022 7:52 AM, Anthony Ortiz wrote:   
   > In the Apple IIe #2 tech notes for DMA, they state the following:   
   >   
   > "...there will be some skew between edges of the 7 M clock and the timing   
   signals from the PAL, such as the edges of 0o or 01. This skew means the 7 M   
   clock edge may rise as much as 20 ns before, or 5 ns after, the 0o falling   
   edge."   
      
   Yeah, that's a pretty ambiguous note.   
      
   > Is this skew only at the 0o falling edge? I ask because I'm using the 7m for   
   timing when to read/write.   
      
   It is my understanding that skew means that one clock signal is delayed   
   in relation to another.  In other words 7M and phase0 had at one time   
   been in sync with each other (that is, the rising edge of phase0 happens   
   at exactly the same time as a rising edge of 7M) but phase0 became   
   delayed because it went through more circuitry than 7M.   
      
   People who know more about hardware than me should jump in here if I'm   
   wrong.   
      
   Anyway, to answer your question, I think that both the rising and   
   falling edges of phase0 would be skewed.   
      
   Charlie   
      
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