From: anthonypaulo@gmail.com   
      
   > You mentioned DMA so I'm thinking that's the timing you are going for.    
   > The IIgs hardware reference says (in reference to cards that work on    
   > other Apple II models) that they will *probably* work if they assert and    
   > remove the /DMA signal within 200 nanoseconds of the rising edge of    
   > phase 0. It also says that normally the IIgs should be running at 1.024    
   > MHz when performing DMAs. There are exceptions to this if you are only    
   > accessing fast ram or rom.    
   > Also with the IIgs you need to set the DMA bank register.    
   >    
   > If you are using a logic device (FPGA, etc.), here is a link to Alex    
   > Freed's verilog code for DMA timing on an Apple IIe which may help:    
   >    
   > https://sourceforge.net/p/jatcb/code/HEAD/tree/dma.v    
   >    
   > Lastly, I like to synchronize all the clocks on the card whether or not    
   > I'm using the 7Mz Apple clock as the system clock or a clock on the card.    
   >    
   > Charlie   
      
   Hey Charlie,   
      
   I'm new to VHDL so I was trying to trigger on both the rising/falling edges of   
   7M to create a counter that offsets from Phase0 rise/fall, that way I could   
   use the counter as a point where to perform certain logic such as read and   
   writes. However, I    
   quickly learned that I know nothing and that just because it's valid VHDL   
   doesn't mean it's synthesizable, lol. I'm just going to create a 100mhz clock   
   so that I have 10ns granularity and use that instead.   
      
   You mention the Carte Blanche; have you done a lot of prototyping with it? Do   
   you have any projects you're working on?   
      
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