From: charlieDOTd@verEYEzon.net   
      
   On 8/11/2022 12:16 AM, Kent Dickey wrote:   
   > In article ,   
   > Charlie   wrote:   
   >> On 8/7/2022 11:24 PM, Kent Dickey wrote:   
   >>> In article ,   
   >>> Charlie   wrote:   
   >>>> On 8/4/2022 7:52 AM, Anthony Ortiz wrote:   
   >>>>> In the Apple IIe #2 tech notes for DMA, they state the following:   
   >>>>>   
   >>>>> "...there will be some skew between edges of the 7 M clock and the   
   >>>> timing signals from the PAL, such as the edges of 0o or 01. This skew   
   >>>> means the 7 M clock edge may rise as much as 20 ns before, or 5 ns   
   >>>> after, the 0o falling edge."   
   > [snip]   
   >>> It's best if you use ph0 to capture bus data, possibly delayed for hold   
   >>> time.  Directly using 7M is problematic, and you'll need to qualify it   
   >>> to avoid metastability issues, and to properly qualify it would seem to   
   >>> take a lot of TTL logic.   
   >>>   
   >>> Kent   
   >>   
   >> By 'qualify' do you mean synchronizing the signals?   
   >> I use two flip-flops to synchronize an Apple II slot signal such as   
   >> phase0 to the card's 'system' clock (which is the Carte Blanche II 'on   
   >> board' clock).   
   >   
   > "Qualify" means using logic gates (for example) to avoid capturing data   
   > in a flip-flop when the data might be changing.  Imagine you have a fast   
   > clock, and want to capture data from a slower domain, but which lines up   
   > with one of your edges.  Have logic create a qualifier signal that is   
   > 0 during this fast clock period, and AND the data with it.  Now, we avoid   
   > latching a signal when it could be changing.   
   >   
   > Metastability is not well understood by most people since almost every   
   > detailed description of how to avoid metastability that I've read has   
   > had at least a small bug.  A common flaw is if you synthesize logic and   
   > don't have a set of timing constraints between clock domains, you may   
   > not be avoiding metastability.  Paths can (and do) take "scenic routes"   
   > if you have no constraints.  "Synthesis" is not an issue with TTL since   
   > you're hand placing components.   
   >   
   > Sometimes you just have to capture data as its changing, and that's   
   > when the 2-3 flip-flops in a row rule come into play.  Note you can really   
   > only do one bit like this, to move a counter requires gray coding and more   
   > care.   
   >   
   > The thing about metastability is it's rare--if you have a problem, it may   
   > be hard to detect in practical testing.   
   >   
   > Kent   
      
   Thanks for your detailed answer.  I've learned some things from it.   
      
   Charlie   
      
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