4066492c   
   From: alawther@spammenot.mac.com   
      
   Anthony Ortiz  wrote:   
   >> So, if I understand correctly, the suggestion was to use an ARM processor   
   >> (cheap and readily available) to support a 32 bit GS/OS , rather than build   
   >> a further extension to the 6502 family, incurring development costs (both   
   >> hardware and software) and then either remaining content with low volumes   
   >> (and high prices) or engaging in a battle to push into a space already   
   >> occupied by the x86 and ARM ‘gorillas’. Even the ARM processors   
   available   
   >> back when this discussion was conducted had enough power to emulate a 6502   
   >> and maybe even a 65816, but one could also have a system with both, similar   
   >> to those machines with Z80 cards.   
   >>   
   >> WDC seem to do sufficiently well continuing to sell 6502 and 65816 chips   
   >> and cores for embedded systems that they haven’t seen the benefit in   
   >> pursuing the 65832 concept.   
   >   
   > Okay, so assuming we're talking about an ARM emulating a 6502, which is   
   > something that has been done and I've done myself, then nothing prevents   
   > us from emulating the 65C816, and if we can do that then we can emulate   
   > the 65832, or create a true 32-bit version of the 65C816. This is what   
   > I'm thinking to do with my little Raspberry Pi project, I'm using my   
   > Raspberry Pi as an accelerator ( ie. a turbo version of the Transwarp)   
   > hence all my questions here about bus timings, but I'd also like to make   
   > it so you can choose the chip to emulate and add a 32-bit mode either by   
   > emulating the 65832 or creating a 32-bit version of the 65C816.   
   >   
      
   The 65C832 as proposed is basically a 32 bit version of the 65C816. In   
   order to implement it you’ll need to make some decisions that WDC never got   
   around to:   
   * opcode and byte count for XFE to switch between bit modes;   
   * how to handle XBA in 32 bit mode (swap the top and bottom 16 bit groups,   
   or bytes 1 and 0 like in 16 bit mode)   
    * whether to clear or preserve the top 16 bits of the A, X, and Y   
   registers when switching between 32 bit and 16 bit modes;   
    * register transfer ops in 32 bit mode (TDC, TSC, TXA, TYA clear top 16   
   bits of C?); and   
    * probably other things I haven’t thought of.   
      
      
   In choosing to emulate a 65C832 you limit yourself to   
    * 8 bit data bus (4 memory cycles to load a 32 bit register)   
    * 24 bit program address space (16Mb limit)   
    * 24 bit data address space (unless you pretend it is an ASIC version with   
   32 bit data address space)   
      
   You’ll also need to develop a new software development tool chain for this   
   ‘preliminary’ processor.   
      
   By comparison, if you chose an ARM coprocessor you’d have the 32 bit   
   address space and tool chain   ready to go.   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)