From: news-1326478115@discworld.dascon.de   
      
   On 2015-12-03, Arachide  wrote:   
   > According to the Freescale PDF documentation about de MC68040, there are   
   > two cloks:   
   >   
   > BCLK: the clock for the bus operations.   
   > PCLK; the clock for the processor operations   
   >   
   > And it is said tha PCLK is twice BCLK, but in the sense that the   
   > designer of the mother board must provide two inputs clocks with one   
   > running at twice the speed of the other.   
   >   
   > The docs then explains that the processor can be clocked at 25, 33 or 40   
   > MHz for PCLK. So BCLK must be 12,5 or 16,5 or 20MHz.   
      
   Exactly. Basically, that means the bus can run at either the same as the   
   internal clock or half the internal clock.  On the Milan, we used the   
   half-speed option (not sure what the hades did), since that nicely fits with   
   60ns EDO memory - running the bus faster than the memory yields no   
   improvement. When using SDRAM (which came available later), running the bus   
   at 60MHz works fine (but I doubt the performance gain will be high, due to   
   the sufficiently large caches of the '060).   
      
   > And the overclocking is hard: I have a 33MHz CPU in my Quadra and an   
   > accelerator that runs fine until 39MHz but then the system hangs at   
   > 40..! 33 to 39 is +18%. Not more.   
      
   Yup - I have the impression the later chips ('040 and '060) are closer to   
   the specified limits than the earlier ones.  I was able to run a 68HC000-16   
   stable at 36MHz (with zero-waitstate fast RAM).  That beast was   
   significantly faster on real work (compiling using PureC) than a 33MHz 68030   
   with only ST-RAM and external caches ...   
      
   cu   
   Michael   
      
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