From: news@druck.org.uk   
      
   On 11/08/2024 22:32, Single Stage to Orbit wrote:   
   > I've got a RISCV baremetal operating system I might bring up on this   
   > device but looking at the datasheet for the RISCV processor used, it's   
   > only got machine mode and user mode, no supervisor mode and no paging.   
   > It does not even support any of the Sv pagetables so that's a   
   > challenge.   
      
   The joys open "open source" CPUs with no standardised feature sets.   
      
   > Most interestingly enough, you can actually boot up with one RISCV core   
   > and one ARM core, two RISCV cores or both ARM cores. Mixed processor   
   > cores that'll be fun to see what we can do with that.   
      
   I think they did that for all the people who keep insisting they should   
   move to the "new future" of RISC V. Now they can find out how badly it   
   compares to a contemporary ARM core.   
      
   ---druck   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)