From: theom+news@chiark.greenend.org.uk   
      
   Richard Kettlewell  wrote:   
   > It’s a slightly odd device, isn’t it?   
   >   
   > If you wanted to explore RISC-V then there’s more flexible options. If   
   > you just wanted a microcontroller for something and didn’t care too much   
   > about CPU architecture then the dual-architecture thing is wasted. Two   
   > entire CPU cores that you don’t get to use.   
      
   Microcontroller RISC-V cores are so small that I presume it's just thrown on   
   there as a test to see how things pan out.  You can do a basic RV32 in a few   
   hundred lines of SystemVerilog and, if it doesn't have its own on-chip   
   memory, it takes pretty minimal area. It's the area for on-chip RAM, on-chip   
   flash, registers, caches and TLBs that costs.   
      
   It sounds like one of their devs had a hobby core on his github and they put   
   it on the chip just because they could.  What I'm more interested in is what   
   QA they did on it and what tools they used.  It's easy to write a core but   
   embarassing if it doesn't do what you think it does[1].  Perhaps the   
   'enabling/disabling' mechanism is a chicken bit to wall it off in case   
   something bad is discovered in it.   
      
   Theo   
      
   [1] https://ghostwriteattack.com/   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)