From: alex.buell@munted.eu   
      
   On Tue, 2024-08-13 at 09:07 -0700, John Larkin wrote:   
   > On Sun, 11 Aug 2024 22:32:38 +0100, Single Stage to Orbit   
   >  wrote:   
   >    
   > > I've got a RISCV baremetal operating system I might bring up on   
   > > this device but looking at the datasheet for the RISCV processor   
   > > used, it's only got machine mode and user mode, no supervisor mode   
   > > and no paging. It does not even support any of the Sv pagetables so   
   > > that's a challenge.    
   >    
   > Our computer thinking evolved when CPUs filled rooms and cost   
   > megabucks, and RAM cost a dollar per byte. Things have changed.   
      
   I grew up with microcomputers that had 32K of RAM and tape players.    
   In some ways I agree, in other ways I disgree.    
      
   We now have glorious displays with a billion colours, mulitmedia   
   capability and different ways to interact with these machines.    
      
   I think it's worth the tradeoffs.    
      
   > Virtual memory worked around the cost of RAM and encouraged   
   > complexity and bloat. Similarly, c calling conventions gave us   
   > hazards.   
   >    
   > It's time to rethink things. CPUs and RAM are cheap, bloated buggy   
   > code is expensive.   
   >    
      
   There's limited forms of memory protection that can mitigate not having   
   a MMU.    
      
   > > Most interestingly enough, you can actually boot up with one RISCV   
   > > core and one ARM core, two RISCV cores or both ARM cores. Mixed   
   > > processor cores that'll be fun to see what we can do with that.    
   >    
   > In real life, done is better than fun.   
      
   Floating point only available with the M33 cores. Hazard3 cores don't.    
   --    
   Tactical Nuclear Kittens   
      
   --- SoupGate-Win32 v1.05   
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