5b150f02
From: joe@user.com
"Fooser" wrote in message
news:56af4faf-f0fe-4f0e-ac54-32319a7ce139@p3g2000pra.googlegroups.com...
> Howdy All.
>
> From what I've gleaned from this newsgroup regarding the Model I CPU &
> Expansion Interface, I've made the following assumptions.
>
> Please correct me if I'm wrong, as I'm trying to build one from parts.
>
> 1) The first EI used a straight though cable and was prone to
> interference... so...
>
> 2) The second EI used a Buffered Cable (no mods to EI or CPU). Still
> had interference problems... so...
>
> 3) The third version used a 6-pin cable dongle that matched one on
> the CPU. (mods on both EI & CPU)
>
> Using this dongled version... does it still require the Buffered
> Cable or a straight through cable?
>
> 4) The fourth version used a completely enhanced EI. Used a straight
> though cable to an unmodified CPU.
>
> I also read that a dongled CPU could use the enhanced EI, but a
> dongled EI required a dongled CPU.
>
> If this is true, and you used a dongled CPU to the enhanced EI,
> would you then use a straight though cable?
>
> There has been quite a few messages along this line, but I have yet to
> figure out when to use the Buffered Cable, and when not to.
>
> If anyone can point me in the right direction, it would be greatly
> appreciated.
>
> Thanks!
There were two EIs. The original design that used RAS MUX and CAS from the
CPU, and the second design that GENERATED the timing signals in the EI. The
second generation EI had a DDU unit that was how the timing signals were
generated.
The original EI originally used a flat but shielded cable. Very stiff, and
problematic unless you kept things still, or had the TRS-80 desk where the
EI and CPU were set in cutouts.
Once timing issues surfaced, the first attempt at a fix was the 'Buffered EI
cable'. This cable was a non-shielded cable with a small PCB in the middle
with buffers to drive the signals across to the EI. The CPU was modified in
two ways to work with this cable. One was to provide power, the other was
to take the RAS MUX and CAS signals and bring thing to the connector with
twisted wire pairs, fed by resistors pairs. In the EI, where the buffered
cable plugged in, traces were cut free, and twisted wires also used to
deliver the signals to where they needed to go with resistor pairs.
It should be noted there were TWO versions of the buffered EI cable. One
version had a 'tab' on the bottom. This was only to allow people with a
'screen printer' to be able to attach to the Buffered EI cable, as it would
no longer work on the EI connector, since the screen printer was a DMA
device, and needed to grab the bus as a bus master for the screen data. It
couldn't do that through the EI cable buffers.
This first fix with the Buffered EI cable became standard production for a
short time on both EI and CPU units.
After the first fixed showed to be ineffective in some cases, a second fix
was developed. This was the 'dongle' version. The buffered cable was still
used, but instead of using the twisted pairs to get to the connector and
then through the cable, they went to a 6-pin DIN connector that hung out of
the CPU case. The EI was essentially the same, the twisted pairs just came
from the DIN dongle.
Finally, the EI was redesigned so that the timing signals were generated
onboard with a digital delay unit (DDU). Once this was done, they went back
to the flat interface cable.
There were other issues, but a lot of what was blamed on timing and the EI
was actually a ton of bad RAM from TI. Real garbage. At the time, NEC had
cheap plastic RAM that supposedly was sub-par but worked perfectly.
Towards the end, I think the CPUs were built so that they would work with
anything. But you couldn't put a buffered cable on a CPU that didn't have
the mods, as there wouldn't be a power feed to the chips in the cable.
--- SoupGate-Win32 v1.05
* Origin: you cannot sedate... all the things you hate (1:229/2)
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