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   sci.electronics.design      Electronic circuit design      143,102 messages   

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   Message 143,061 of 143,102   
   Phil Hobbs to john larkin   
   Re: Negative Supply Rejection Sucks   
   23 Feb 26 22:29:16   
   
   From: pcdhSpamMeSenseless@electrooptical.net   
      
   On 2026-02-23 22:16, john larkin wrote:   
   > On Tue, 24 Feb 2026 00:46:22 -0000 (UTC), Phil Hobbs   
   >  wrote:   
   >   
   >> john larkin  wrote:   
   >>> On 23 Feb 2026 22:57:00 GMT, Uwe Bonnes   
   >>>  wrote:   
   >>>   
   >>>> john larkin  wrote:   
   >>>> ...   
   >>>>> That's about 12 power supplies!   
   >>>>>   
   >>>>> My new gadget, the PPG (Precision Pulse Generator) only needs about 7.   
   >>>>>   
   >>>>> Interestingly, the most critical one, for noise and drift, is the 1.2   
   >>>>> volt FPGA core supply. 100uV changes the prop delay more than I like.   
   >>>>>   
   >>>>>   
   >>>> Consider some stabilization loop. Some FPGA TDC design use similar   
   >>>> approaches.   
   >>>   
   >>> I'm designing basically an economy DDG, digital delay generator. So   
   >>> I'm not investing engineering hours or parts cost on extreme   
   >>> performance.   
   >>>   
   >>> So I'll just make the 1.2v supply as good as we reasonably can and   
   >>> sell whatever it does.   
   >>>   
   >>> Prop delay in the FPGA is about inverse on core power supply voltage.   
   >>> If the supply is noisy, I don't think we could compensate for that in   
   >>> real time.   
   >>>   
   >>> We will know the PCB temperature so maybe we'll compensate for that a   
   >>> little. That would be a quick test and a bit of code.   
   >>>   
   >>   
   >> Using a backwards PLL to regulate the supply would be pretty amusing,   
   >> though, you have to admit.   
   >>   
   >> Cheers   
   >>   
   >> Phil Hobbs   
   >   
   > Yes. We couldn't compare the FPGA to an external delay line (they   
   > aren't very good) so we'd need a clever (and affordable) way to   
   > compare a prop delay to a clock.   
   >   
   > Of course, every time you compile an FPGA design it may change the   
   > routing radically.   
   >   
   > Sometimes the optimizer decides that you really don't need to do   
   > something at all.   
   >   
   > But amusing is the enemy of cheap and done. That's a real problem in   
   > this industry.   
   >   
   >   
   You're no fun anymore. ;)   
      
   Cheers   
      
   Phil Hobbs   
      
      
      
   --   
   Dr Philip C D Hobbs   
   Principal Consultant   
   ElectroOptical Innovations LLC / Hobbs ElectroOptics   
   Optics, Electro-optics, Photonics, Analog Electronics   
   Briarcliff Manor NY 10510   
      
   http://electrooptical.net   
   http://hobbs-eo.com   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)   

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