From: jl@glen--canyon.com   
      
   On Tue, 24 Feb 2026 09:59:25 +0100, Gerhard Hoffmann    
   wrote:   
      
   >Am 24.02.26 um 04:16 schrieb john larkin:   
   >   
   >   
   >> Yes. We couldn't compare the FPGA to an external delay line (they   
   >> aren't very good) so we'd need a clever (and affordable) way to   
   >> compare a prop delay to a clock.   
   >   
   >I've built a switchable delay line from a reel of semi rigid coax,   
   >heaps of SMA connectors and 3 pairs/stages of 1-to-6 coax relays.   
   >The 1-to-6 relays were surprisingly cheap at ham radio meetings,   
   >there exist not many apps for them.   
   >   
   >The delay line could bring anything between 4 and 100 MHz into   
   >phase quadrature for phase noise measurements.   
   >It was a lot of work soldering SMAs, verifying / trimming cable   
   >lengths on the TDR and packing everything into a 19" crate.   
   >   
   >Exactly when I was done, I got hold of a Time Pod that could   
   >do everything with 20 dB better pn resolution thanks to cross   
   >correlation.   
   >   
   >> Of course, every time you compile an FPGA design it may change the   
   >> routing radically.   
   >   
   >Back in Xilinx XC3020 times, a friend did his FPGA design   
   >barefoot with the XACT editor by hand and he locked down every   
   >connection and transmission gate. He ran out of luck when the next   
   >chip delivery showed better but different timings.   
   >   
   >He is a chip broker now.   
   >   
   >Cheers,  Gerhard   
   >   
   >   
      
   There are some SMT 90-cent DPDT relays that are pretty good up to   
   around 5 GHz. One could make a switchable delay line from them.   
      
   The challenge would be to get lots of bits with monotonic - or even   
   calibrated - delay.   
      
      
   John Larkin   
   Highland Tech Glen Canyon Design Center   
   Lunatic Fringe Electronics   
      
   --- SoupGate-Win32 v1.05   
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