XPost: sci.math, comp.lang.prolog   
   From: janburse@fastmail.fm   
      
   Hi,   
      
   I am not saying anything. Thats the definition of PRAM.   
   Whats wrong with you, are you a 5 year old moron.   
   I am only citing a theoretical computer science model:   
      
   - Concurrent read concurrent write (CRCW)—multiple   
   processors can read and write. A CRCW PRAM is sometimes   
   called a concurrent random-access machine.   
   https://en.wikipedia.org/wiki/Parallel_RAM   
      
   Technically with multi-channel memory nowadays, it   
   doesn't need locks on the hardware level, only tiny   
   serialization, could even happen outside of the CPU.   
      
   So if you drop some barrier requirements, you could   
   really have the chaos of a PRAM, for worse or   
   for better. I think you need to accept that,   
      
   even if its to big to fit in your tiny squirrel brain.   
      
   Bye   
      
   P.S.: "effectively CREW, since only one write per address at   
   a time", it will just block the other cores? Short answer:   
   Yes — if two cores try to write the same address, one   
      
   of them is forced to stall (block) until the other completes.   
   In real hardware, the effect can mimic CRCW behavior over   
   a short time window, even though it’s not truly simultaneous.   
      
   this blocking usually happens in the cache-coherence   
   system, not at DRAM. Modern CPUs use MESI/MOESI. It happens   
   over a small interval [t₁, t₂] dictated by cache coherence.   
      
    From the POINT OF VIEW OF AN ALGORITHM, it’s “CRCW enough.”   
      
      
   Bosephis Otlesnov schrieb:   
   > Mild Shock wrote:   
   >   
   >> What are you, a 5 year old moron?   
   >>   
   >> There are millions of algorithm that use volatile variables. Just look   
   >> at the Java code base.   
   >>   
   >> But I was not refering to multi-threading, I was refering to PRAM for   
   >> matrix operations.   
   >   
   > i thought you said you wanna read and write parallel to RAM, aka PRAM, let   
   > me see.. zum zum zum, yeah, you said that. Take a lock at timing   
   > requirements for a read/write cycle, deadlines etc, shared memory or not,   
   > fucking idiot.   
   >   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)