From: d1@d1.d1   
      
   Hello,   
      
   Read this:   
      
      
   About “write combining store buffers”..   
      
   Modern CPUs employ lots of techniques to counteract the latency cost   
   of going to main memory.  These days CPUs can process hundreds of   
   instructions in the time it takes to read or write data to the DRAM   
   memory banks.   
      
   The major tool used to hide this latency is multiple layers of SRAM   
   cache.  In addition, SMP systems employ message-passing protocols to   
   achieve coherence between caches.  Unfortunately CPUs are now so fast   
   that even these caches cannot keep up at times.  So to further hide this   
   latency a number of less well-known buffers are used.   
      
   This article explores “write combining store buffers” and how we can   
   write code that uses them effectively.   
      
   Read more here:   
      
   https://www.i-programmer.info/programming/hardware/3114-write-combining.html   
      
      
      
   Thank you,   
   Amine Moulay Ramdane.   
      
   --- SoupGate-Win32 v1.05   
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